Category |
Multi-core processor |
Explicit Data Graph Execution |
Vaakya Architecture |
System bus model |
Processor-in-memory |
Harvard architecture |
Wel come
"Processor in memory" or PIM technology and architecture, parallel computer architecture research and development has become one of the most important areas. The one to deal with irregular data structures and traditional systems as a way to speed signal processing is developed. Smart for ultra-scale computing systems in a hybrid technology multithreaded architecture, resource management is considered as the spatial scales of memory, as a basis for calculating received, and more recently as a means of petaflops performance is. PIM recent advances in semiconductor manufacturing processes, and enable the integration of DRAM cell block on a single chip CMOS logic exploits.
Internal memory, a range of 100 Gbit / s return 16 MB of memory chip with a capacity of 10 votes (32-bit operands), the possible number of buffer blocks to order direct memory access to the benefits of the structure of the PIM processing logic . To stay in the chip because of efficiency, power consumption comparable to a conventional microprocessor-based system performance may be orders of magnitude lower than. But great progress in performance resulting from the tight coupling of the hundreds or thousands of PIM chips matrices, either alone or in combination with external microprocessor. These systems offer a low-level peak can be performed on the next two years and possibly a petaflops teraflops, for some applications at least five years.
PIM the extraordinary ability to realize the challenge of matrices only chip and processor architecture is the interesting problem of infrastructure, but also the synthesis of PIM coordination over a million processors in concert to solve a parallel methodology is not Applications to participate. A variety of PIM is not only an MPP, a new organization, a new balance of processing and memory. Our campaign throughout local and global emergent behavior that is highly parallel computing system implementation and PIM processors and chips that controls the relationship is a direct reflection of a general model. Should the computing paradigm of the system, including the self-processing ability of the individual parts of the local system is needed for treatment means. Cooperation incompatible elements are achieved through the combined performance models.